Prog sue ise pack ixilinx

Bonjour,

voici mon code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity registre is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
Din : in STD_LOGIC_VECTOR (3 downto 0);
Dout : out STD_LOGIC_VECTOR (3 downto 0));
end registre;

architecture Behavioral of registre is
--signal S: STD_LOGIC_VECTOR (3 downto 0);

component flip-flop is
Port ( reset : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC;
clk : in STD_LOGIC);
end component;

begin
Ul:flip-flop;
port map (reset,Din(0),clk,Dout(0));
U2:flip-flop;
port map (reset,Din(1),clk,Dout(1));
U3:flip-flop;
port map (reset,Din(2),clk,Dout(2));
U4:flip-flop;
port map (reset,Din(3),clk,Dout(3));

end Behavioral;

g compend pas c quoi l'erreur il m'affiche

ERROR:HDLParsers:164 - "C:/TP_CAO/flip-flop/registre.vhd" Line 40. parse error, unexpected MINUS, expecting END