VHDL

Bonjour,

J'ai un probleme pour instancier mon programme ci dessous, je veux faire un composant qui mémorise les sorties de quatre registre comme suit, mais l'instanciation ne marche pas???

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity reg1 is
port( D1:in std_logic_vector(3 downto 0);
clock:in std_logic;
Q1:out std_logic_vector(3 downto 0)
);
end reg1;

architecture V1 of reg1 is
begin
process(clock)
begin
if Rising_Edge(clock) then
Q1(0) <= D1(0);
Q1(1) <= D1(1);
Q1(2) <= D1(2);
Q1(3) <= D1(3);
end if;
end process;
end architecture;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reg2 is
port( D2:in std_logic_vector(3 downto 0);
clock:in std_logic;
Q2:out std_logic_vector(3 downto 0)
);
end reg2;

architecture V1 of reg2 is
begin
process(clock)
begin
if Rising_Edge(clock) then
Q2(0) <= D2(0);
Q2(1) <= D2(1);
Q2(2) <= D2(2);
Q2(3) <= D2(3);
end if;
end process;
end architecture;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reg3 is
port( D3:in std_logic_vector(3 downto 0);
clock:in std_logic;
Q3:out std_logic_vector(3 downto 0)
);
end reg3;

architecture V1 of reg3 is
begin
process(clock)
begin
if Rising_Edge(clock) then
Q3(0) <= D3(0);
Q3(1) <= D3(1);
Q3(2) <= D3(2);
Q3(3) <= D3(3);
end if;
end process;
end architecture;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reg4 is
port( D4:in std_logic_vector(3 downto 0);
clock:in std_logic;
Q4:out std_logic_vector(3 downto 0)
);
end reg4;

architecture V1 of reg4 is
begin
process(clock)
begin
if Rising_Edge(clock) then
Q4(0) <= D4(0);
Q4(1) <= D4(1);
Q4(2) <= D4(2);
Q4(3) <= D4(3);
end if;
end process;
end architecture;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity stockage is
port( Busint:in std_logic_vector(3 downto 0);
Detectar:in std_logic;
Buscode:out std_logic_vector(15 downto 0)
);
end stockage;

architecture directe of stockage is
signal Qout: std_logic_vector(15 downto 0);
begin
st1: entity work.reg1(V1) portmap(D1=>Busint,Detectar=>clock);
st2: entity work.reg2(V1) portmap(Q1=>D2,Detectar=>clock);
st3: entity work.reg3(V1) portmap(Q2=>D3,Detectar=>clock);
st4: entity work.reg4(V1) portmap(Q3=>D4,Detectar=>clock);

process(Detectar)
begin
if Rising_Edge(Detectar) then
Qout(3 to 0) <= Q1;
Qout(7 to 4) <= Q2;
Qout(11 to 8) <= Q3;
Qout(15 to 12) <= Q4;
end if;
Buscode <= Qout;

end process;

end architecture;

Merci pour la reponse.